Chapter 1: Introduction to SystemVerilog
Chapter 2: SystemVerilog Declaration Spaces
Example 2-1: A package definition ...9
Example 2-2: Explicit package references using the :: scope resolution operator .10
Example 2-3: Importing specific package items into a module 11
Example 2-4: Using a package wildcard import 13
Example 2-5: External declarations in the compilation-unit scope (not synthesizable) 15
Example 2-6: Package with conditional compilation (file name: definitions.pkg) 21
Example 2-7: A design file that includes the conditionally-compiled package file 23
Example 2-8: A testbench file that includes the conditionally-compiled package file .23
Example 2-9: Mixed declarations of time units and precision (not synthesizable) 34
Chapter 3: SystemVerilog Literal Values and Built-in Data Types
Example 3-1: Relaxed usage of variables 53
Example 3-2: Illegal use of variables ..54
Example 3-3: Applying reset at simulation time zero with 2-state types 65
Chapter 4: SystemVerilog User-Defined and Enumerated Types
Example 4-1: Directly referencing typedef definitions from a package ..77
Example 4-2: Importing package typedef definitions into $unit ...78
Example 4-3: State machine modeled with Verilog ‘define and parameter constants 79
Example 4-4: State machine modeled with enumerated types .81
Example 4-5: Using special methods to iterate through enumerated type lists ..91
Example 4-6: Printing enumerated types by value and by name ...92
Chapter 5: SystemVerilog Arrays, Structures and Unions
Example 5-1: Using structures and unions ..112
Example 5-2: Using arrays of structures to model an instruction register ..129
Chapter 6: SystemVerilog Procedural Blocks, Tasks and Functions
Example 6-1: A state machine modeled with always procedural blocks 145
Example 6-2: A state machine modeled with always_comb procedural blocks ...147
Example 6-3: Latched input pulse using an always_latch procedural block 151
Chapter 7: SystemVerilog Procedural Statements
Example 7-1: Using SystemVerilog assignment operators 175
Example 7-2: Code snippet with unnamed nested begin...end blocks ...192
Example 7-3: Code snippet with named begin and named end blocks ..193
Chapter 8: Modeling Finite State Machines with SystemVerilog
Example 8-1: A finite state machine modeled with enumerated types (poor style) ..208
Example 8-2: Specifying one-hot encoding with enumerated types .210
Example 8-3: One-hot encoding with reversed case statement style .212
Example 8-4: Code snippet with illegal assignments to enumerated types 216
Chapter 9: SystemVerilog Design Hierarchy
Example 9-1: Nested module declarations ..228
Example 9-2: Hierarchy trees with nested modules 231
Example 9-3: Simple netlist using Verilog’s named port connections ..235
Example 9-4: Simple netlist using SystemVerilog’s .name port connections 239
Example 9-5: Simple netlist using SystemVerilog’s .* port connections .243
Example 9-6: Netlist using SystemVerilog’s .* port connections without aliases ..248
Example 9-7: Netlist using SystemVerilog’s .* connections along with net aliases .249
Example 9-8: Passing structures and arrays through module ports ...252
Example 9-9: Passing a reference to an array through a module ref port ...255
Example 9-10: Polymorphic adder using parameterized variable types ..261
Chapter 10: SystemVerilog Interfaces
Example 10-1: Verilog module interconnections for a simple design .264
Example 10-2: SystemVerilog module interconnections using interfaces ...270
Example 10-3: The interface definition for main_bus, with external inputs ..274
Example 10-4: Using interfaces with .* connections to simplify complex netlists ..275
Example 10-5: Referencing signals within an interface .280
Example 10-6: Selecting which modport to use at the module instance .283
Example 10-7: Selecting which modport to use at the module definition 284
Example 10-8: A simple design using an interface with modports .287
Example 10-9: Using modports to select alternate methods within an interface 291
Example 10-10:Exporting a function from a module through an interface modport ...294
Example 10-11:Exporting a function from a module into an interface 294
Example 10-12:Using parameters in an interface ...297
Chapter 11: A Complete Design Modeled with SystemVerilog
Example 11-1: Utopia ATM interface, modeled as a SystemVerilog interface .306
Example 11-2: Cell rewriting and forwarding configuration ...307
Example 11-3: ATM squat top-level module 309
Example 11-4: Utopia ATM receiver ..315
Example 11-5: Utopia ATM transmitter ..318
Example 11-6: UtopiaMethod interface for encapsulating test methods .321
Example 11-7: CPUMethod interface for encapsulating test methods 322
Example 11-8: Utopia ATM testbench 323
Chapter 12: Behavioral and Transaction Level Modeling
Example 12-1: Simple memory subsystem with read and write tasks 333
Example 12-2: Two memory subsystems connected by an interface ..335
Example 12-3: TLM model with bus arbitration using semaphores ...338
Example 12-4: Adapter modeled as a module ...341
Example 12-5: Simplified Intel Multibus with multiple masters and slaves 342
Example 12-6: Simple Multibus TLM example with master adapter as a module 343
Example 12-7: Simple Multibus TLM example with master adapter as an interface .348