資料介紹
The SN74LVTH322374 is a 32-bit edge-triggered D-type flip-flop with 3-state outputs designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
This device can be used as four 8-bit flip-flops, two 16-bit flip-flops, or one 32-bit flip-flop. On the positive transition of the clock (CLK), the Q outputs of the flip-flop take on the logic levels set up at the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without need for interface or pullup components.
OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
The outputs, which are designed to source or sink up to 12 mA, include equivalent 22- series resistors to reduce overshoot and undershoot.
Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
When VCC is between 0 and 1.5 V, the devices are in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
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- 具有3態(tài)輸出的3.3-V ABT 16位緩沖器/驅(qū)動(dòng)器SN54LVTH162541 SN74LVTH162541數(shù)據(jù)表
- 具有3態(tài)輸出的3.3-V ABT 16位緩沖器/驅(qū)動(dòng)器SN74LVTH16244A-EP數(shù)據(jù)表
- 具有3態(tài)輸出的3.3-V ABT 16位總線(xiàn)收發(fā)器SN74LVTH16245A-EP數(shù)據(jù)表
- 具有3態(tài)輸出的3.3-V ABT 16位緩沖器/驅(qū)動(dòng)器SN54LVTH16240 SN74LVTH16240數(shù)據(jù)表
- 具有3態(tài)輸出的3.3-V ABT 16位邊緣放大D型觸發(fā)器SN54LVTH162374 SN74LVTH162374數(shù)據(jù)表
- 3.3-V ABT 16位透明D型三態(tài)輸出鎖存器SN54LVTH162373 SN74LVTH162373數(shù)據(jù)表
- 3.3-V ABT 16位透明D型三態(tài)輸出鎖存器SN54LVTH16373 SN74LVTH16373 數(shù)據(jù)表
- 具有3態(tài)輸出的3.3伏ABT八路總線(xiàn)收發(fā)器SN54LVTH2245 SN74LVTH2245數(shù)據(jù)表
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- SN74LVTH32373,pdf(3.3-V ABT 32
- SN74LVTH32374,pdf(3.3-V ABT 32
- SN74LVTH32245,pdf(3.3-V ABT 32
- SN74LVTH16245A-Q1,pdf(3.3-V AB
- SN74LVTH32244,pdf93.3-V ABT 32
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